Example: A reprogrammable small Model-1¶
This is work in progress and here comes some more pictures and description.
Well there¶
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224 225 226 227 228 229 230 231 232 233 234 235 236 237 238 239 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255 256 257 258 259 260 261 262 263 264 265 266 267 268 269 270 271 272 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 289 290 291 292 293 294 295 296 297 298 299 300 301 302 303 304 305 306 307 308 309 310 311 312 313 314 315 316 317 318 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 339 340 341 342 343 344 345 346 347 348 349 350 351 352 353 354 355 356 357 358 359 360 361 362 363 364 365 366 367 368 369 370 371 372 373 374 375 376 377 378 379 380 381 382 383 384 385 386 387 388 389 390 391 392 393 394 395 396 397 398 399 400 401 402 403 404 405 406 407 408 409 410 411 412 413 414 415 416 417 418 419 420 421 422 423 424 425 426 427 428 429 430 431 432 433 434 435 436 437 438 439 440 441 442 443 444 445 446 447 448 449 450 451 452 453 454 455 456 457 458 459 460 461 462 463 464 465 466 467 468 469 470 471 472 473 474 475 476 477 478 479 480 481 482 483 484 485 486 487 488 489 490 491 492 493 494 495 496 497 498 499 500 501 502 503 504 505 506 507 508 509 510 511 512 513 514 515 516 517 518 519 520 521 522 523 524 525 526 527 528 529 530 531 532 533 534 535 536 537 538 539 540 541 542 543 544 545 546 547 548 549 550 551 552 553 554 555 556 557 558 559 560 561 562 563 564 565 566 567 568 569 570 571 572 573 574 575 576 577 578 579 580 581 582 583 584 585 586 587 588 589 590 591 592 593 594 595 596 597 598 599 600 601 602 603 604 605 606 607 608 609 610 611 612 613 614 615 616 617 618 619 620 621 622 623 624 625 626 627 628 629 630 631 632 633 634 635 636 637 638 639 640 641 642 643 644 645 646 647 648 649 650 651 652 653 654 655 656 657 658 659 660 661 662 663 664 665 666 667 668 669 670 671 672 673 674 675 676 677 678 679 680 681 682 683 684 685 686 687 688 689 690 691 692 693 694 695 696 697 698 699 700 701 702 703 704 705 706 707 708 709 710 711 712 713 714 715 716 717 718 719 720 721 722 723 724 725 726 727 728 729 730 731 732 733 734 735 736 737 738 739 740 741 742 743 744 745 746 747 748 749 750 751 752 753 754 755 756 757 758 759 760 761 762 763 764 765 766 767 768 769 770 771 772 773 774 775 776 777 778 779 780 781 782 783 784 785 786 787 788 | # This is a YAML description file for a machine.
# A poor man's Analog HDL (should use Verilog HDLs instead)
#
# Copyright (c) 2020 anabrid GmbH
# Contact: https://www.anabrid.com/licensing/
#
# This file is part of the FPAA module of the PyAnalog toolkit.
#
# ANABRID_BEGIN_LICENSE:GPL
# Commercial License Usage
# Licensees holding valid commercial anabrid licenses may use this file in
# accordance with the commercial license agreement provided with the
# Software or, alternatively, in accordance with the terms contained in
# a written agreement between you and Anabrid GmbH. For licensing terms
# and conditions see https://www.anabrid.com/licensing. For further
# information use the contact form at https://www.anabrid.com/contact.
#
# GNU General Public License Usage
# Alternatively, this file may be used under the terms of the GNU
# General Public License version 3 as published by the Free Software
# Foundation and appearing in the file LICENSE.GPL3 included in the
# packaging of this file. Please review the following information to
# ensure the GNU General Public License version 3 requirements
# will be met: https://www.gnu.org/licenses/gpl-3.0.html.
# For Germany, additional rules exist. Please consult /LICENSE.DE
# for further agreements.
# ANABRID_END_LICENSE
#
title: AP/M-1 Mini
description: |
This file describes the hardware layout of a particular Analog Paradigm
Model-1 machine with software-definable XBAR in the smallest setup,
containing SUM8, INT4, MUL4, DPT32 (and of course XBAR, HC).
The number of Summers limits the number of negating-macro elements
which can be built. The configurable parts show what can be done
SUM8.1 => 1 x SUM2m
SUM8.2 => 0.5 SUM2pm
SUM8.3 => 0.5 SUM2pm
SUM8.4 => 0.5 SUM2pm
SUM8.5 => 0.5 SUM2pm
SUM8.6 => 1 x INT2pm
SUM8.7 => 1 x INT2pm, leaving 1 x INT2m
SUM8.8 => 1 x MUL2pm, leaving 1 x MUL2m
In total 8 computing elements. See configurable_parts for the formal
definition.
configurable_parts:
# naming follows the HyCon YML file, part "elements"
INT0-0:
type: INTpinv
address:
out: 0x0160 # integrator INT8.1
inv: 0x0123 # summer SUM8.4 as inverter
INT0-1:
type: INTpinv
address:
out: 0x0161 # integrator INT8.2
inv: 0x0126 # summer SUM8.7 as inverter
INT0-2:
type: INTp
address:
out: 0x0162 # integrator INT8.3
MLT0-0: # HyCon calls it MLT8-0
type: MULpinv
address:
out: 0x0100 # multiplier MUL4.1
inv: 0x0127 # summer SUM8.8 as inverter
MLT0-1: # HyCon calls it MLT8-1
type: MULpinv
address:
out: 0x0100 # multiplier MUL4.2
SUM0-0:
type: SUMpinv
address:
out: 0x0120 # summer SUM8.1
inv: 0x0124 # summer SUM8.5 as inverter (is below 1)
SUM0-1:
type: SUMpinv
address:
out: 0x0121 # summer SUM8.2
inv: 0x0125 # summer SUM8.6 as inverter (is below 2)
SUM0-2:
type: SUMp
address:
out: 0x0122 # summer SUM8.3
PlusOne:
description: |
Positive supply voltage/machine unit, also refered to as Vcc or Vdd,
i.e. +10V in this machine.
cannot_be_allocated: True
type: ConstantVoltage
input: [ +1 ]
MinusOne:
description: |
Negative supply voltage/machine unit, also refered to as Vss,
i.e. -10V in this machine.
cannot_be_allocated: True
type: ConstantVoltage
input: [ -1 ]
None:
description: See description of NoneType
cannot_be_allocated: True
type: NoneType
# We currently not make (yet) use of these levels anywhere, but they
# are later required for evaluating MUL's, for instance.
logic:
boolean: [ True, False ]
machine_units: [ +1, -1 ]
voltage_range: [ +10, -10 ]
voltage_unit: V
DGND_voltage: 0 # won't this be different
AGND_voltage: 0 # on the chip?
entities:
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# Elementary building blocks of Model-1 Computer
#
## # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
DPT:
type: elementary
description: |
A single digital potentiometer (part of a DPT24 or HC module).
computes:
vs: vs=v0*v
input:
- { name: v0, type: numeric, range: [0, 1] }
- { name: v, type: analog }
output:
- { name: vs, type: analog }
SUM:
type: elementary
description: |
A single summer (part of a SUM8 module).
The summer is a negating summer featuring
* three inputs of weight a=10 (input prefix "d" for "decade") and
* three inputs of weight a= 1 (input prefix "u" for "unit")
We are lazy so we only describe two input lines each.
We dont model the summing junction (SJ) yet.
computes:
out: out = -(10*d1 + 10*d2 + u1 + u2)
input:
- { name: d1, type: analog }
- { name: d2, type: analog }
- { name: u1, type: analog }
- { name: u2, type: analog }
output:
- name: out
type: analog
description: Output of negating summer
default_inputs: { d1: None, d2: None, u1: None, u2: None }
INT:
type: elementary
description: |
A single integrator (one of the INT4 module).
The integrator is an (implicite negating summing) intergrator
featuring
* three inputs of weight a=10 (input prefix "d" for "decade") and
* three inputs of weight a= 1 (input prefix "u" for "unit")
We are lazy so we only describe two input lines each.
For the moment, we dont model/make use of ModeIC and ModeOP.
computes:
out: out = integral(-10*d1(t) - 10*d2(t) - u1(t) - u2(t), t)
input:
- { name: d1, type: analog }
- { name: d2, type: analog }
- { name: u1, type: analog }
- { name: u2, type: analog }
- name: ic
type: analog
description: Initial condition
output:
- name: out
type: analog
description: Output of integral
default_inputs: { d1: None, d2: None, u1: None, u2: None, ic: None }
MUL:
type: elementary
description: |
A single multiplier (one of the MLT8 module).
Remember that multiplication is implemented normalized. For instance,
if machine voltage is level=+10V (actually +-10V), the multiplication
computes res = (a/level * b/level)*level in order to make sure
|res|<10V.
-> In order to decouple analog programming from the machine where
it runs, the normalization should be implemented in the
compilation step!
input:
- { name: a, type: analog }
- { name: b, type: analog }
output:
- { name: out, type: analog }
computes:
out: out = a*b/voltage_level
default_inputs: [ a: PlusOne, b: PlusOne ] # useful?
CMPad:
description: |
The left part of a CMP4 comparator (analog2digital),
i.e. a treshold based binarization.
computes:
res: res = a+b>0
input:
- { name: a, type: analog }
- { name: b, type: analog }
output:
- { name: res, type: digital }
CMPda:
description: |
The right part of a CMP4 comparator (digital2analog),
i.e. a single electronic switch switching between two analog
signals.
computes:
u: u = if(i, a, b)
input:
- { name: i, type: digital } # boolean
- { name: a, type: analog }
- { name: b, type: analog }
output:
- { name: u, type: analog }
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# Macro computing elements plugged together by elementary ones
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
SUMp:
type: macro
description: |
A single summer (SUM8 part) and two digital potentiometers.
We only use weights a=10 from the summer.
The flow chart is given by:
(a0)----+
|
v
(a)->[DPTa]--(as)-->[10| ]
[ | SUMo ]---> out
(b)->[DPTb]--(bs)-->[10| ]
^
|
(b0)----+
computes:
out: out = -(a0*a + b0*b)
input:
- name: a0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: a
type: analog
- name: b0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: b
type: analog
output:
- name: out
type: analog
description: Output of negating summer
default_inputs:
a: None
b: None
a0: 0
b0: 0
internal_wires:
- name: as
type: analog
description: Scaled a (output of DPTa)
- name: bs
type: analog
description: Scaled b (output of DPTb)
partlist:
DPTa:
type: DPT
input: [ a0, a ]
output: as
DPTb:
type: DPT
input: [ b0, b ]
output: bs
SUMo:
type: SUM
input: { d1: as, d2: bs }
output: out
# These "is a"-relations should allow using elements instead of others
is_a:
SUM:
description: Can mimic a simple summer when having both DPTs = 1.
default_inputs: [a0: 1, b0: 1]
DPT:
description: Can mimic a simple potentiometer when not summing at all.
default_inputs: [a: None, b: None, b0: 0]
MULp:
type: macro
description: |
A simple macro element made of a single multiplier (MLT8) and two
digital potentiometers (on DPT24).
The flow chart is similar to SUMp:
(a0)----+
|
v
(a)->[DPTa]--(as)-->[ ]
[ MULo ]---> out
(b)->[DPTb]--(bs)-->[ ]
^
|
(b0)----+
input:
- { name: a0, type: digital }
- { name: a, type: analog }
- { name: b0, type: digital }
- { name: b, type: analog }
output:
- { name: out, type: analog }
computes:
out: out = a0*a*b0*b/voltage_level
default_inputs:
a: PlusOne
b: PlusOne
a0: 0
b0: 0
internal_wires:
- name: as
type: analog
description: Scaled a (output of DPTa)
- name: bs
type: analog
description: Scaled b (output of DPTb)
partlist:
DPTa:
type: DPT
input: [ a0, a ]
output: as
DPTb:
type: DPT
input: [ b0, b]
output: bs
MULo:
type: MUL
input: [as, bs]
output: out
is_a:
MUL:
description: Can mimic a simple multiplier when having both DPTs = 1.
default_inputs: [a0: 1, b0: 1]
# DPT: would be ironic since MLT also multiplies. Would rather compute MLT(DPT(x,PlusOne),PlusOne)
INTp:
type: macro
description: |
A macro component made of an integrator (one in the INT4 module)
and three potentiometers (two shall be implemented on the DPT24,
one on the HC, but that doesn't matter at this stage).
The integrator is an (implicite negating summing) intergrator
with two inputs. For the moment, we dont make use of ModeIC and
ModeOP. All inputs use weight a=10.
In the moment, the ICs are realized by one potentiometer and
a comparator. The compiler creates the binary sign which steers
the comparator and is outputted by the Hybrid Controller (HC).
The summer is a (negating) summer with a single input.
The summer uses weight a=1.
Neither in integrator nor summer, we make use of the SJ.
The flow chart looks like
ic ----------------------------+
|
HC digital output, |
icSign -----+ |
| switches | controls
v v
+1 -(p1)->[ SignGen ]-(pm)->[DPTic] (HC DPT)
-1 -(m1)->[ (CMPda) ] |
(aic)
a0 ------+ |
| controls | sets IC
v v
a ->[DPTa]---(as)--->[10| ]
[ Integrator ]----> out
b ->[DPTb]---(bs)--->[10| ]
^
| controls
b0 ------+
computes:
out: out = -integral( a0*a(t) + b0*b(t), t)
input:
- name: a0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: a
type: analog
- name: b0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: b
type: analog
- name: icSign
type: boolean
description: Sign of initial condition value
- name: ic
type: numeric
description: Value for initial condition
range: [0, 1]
output:
- name: out
type: analog
description: Output of integral
default_inputs:
a: None
b: None
a0: 0
b0: 0
icSign: True
ic: 0
internal_wires:
- name: as
type: analog
description: Scaled a (output of DPTa)
- name: bs
type: analog
description: Scaled b (output of DPTb)
- name: aic
type: analog
description: Analog Initial conditions (output of Comparator and multiplied by HC DPT)
- name: pm
type: analog
description: Plus or Minus, depending on the sign bit
partlist:
DPTa:
type: DPT
input: [ a0, a ]
output: as
DPTb:
type: DPT
input: [ b0, b]
output: bs
SignGen:
type: CMPda0
input:
i: icSign
a: PlusOne
b: MinusOne
output: pm
DPTic:
type: DPT # but shall be implemented on HC for clarity
input: [ ic, pm ]
output: aic
INTo:
type: INT
input: { d1: as, d2: bs, ic: aic }
output: out
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# Macro elements with attached inverter (negation)
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
SUMpinv:
type: macro
is_a:
SUMp:
description: |
Can mimic a single potentiometered summer. Just ignore the inv output.
description: |
A macro component made of two summers (SUM8 module) and two digital
potentiometers (on DPT24). It is an easy extension of the SUMp
module, the flow chart is just:
+-------+
a0 -->| | +--[ 1| SUMinv ]-> inv
a -->| SUMp | |
b0 -->| |--------+----------------> out
b -->| |
+-------+
Remember, the summer SUMo in SUMp uses weights a=10, while the
inverting summer SUMinv uses weight a=1.
computes:
out: out = a0*a + b0*b
inv: inv = -(a0*a + b0*b)
input:
- name: a0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: a
type: analog
- name: b0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: b
type: analog
output:
- name: out
type: analog
description: Output of minus operation (actual summer output)
- name: inv
type: analog
description: Output of plus operation (negation of summer output)
default_inputs:
a: None
b: None
a0: 0
b0: 0
partlist:
MainSummer:
type: SUMp
input: [ a0, a, b0, b ]
output: out
SUMinv:
type: SUM
input: { u1: out }
output: inv
MULpinv:
type: macro
description: |
Extension of MUL2m with two outputs, where one is negated, thus
requiring an internal summer.
Flow chart is just:
+-------+
a0 -->| | +--[ 1| SUMinv ]-> inv
a -->| MULp | |
b0 -->| |--------+----------------> out
b -->| |
+-------+
input:
- name: a0
type: digital
- name: a
type: analog
- name: b0
type: digital
- name: b
type: analog
output:
- name: out
type: analog
- name: inv
type: analog
computes:
out: out = a0*a*b0*b/voltage_level
inv: inv = -a0*a*b0*b/voltage_level
default_inputs:
a: PlusOne
b: PlusOne
a0: 0
b0: 0
partlist:
Multiplier:
type: MULp
input: [ a0, a, b0, b ]
output: out
SUMinv:
type: SUM
input: { u1: out }
output: inv
INTpinv:
type: macro
is_a:
INTp:
description: |
Can mimic a single potentiometered integrator. Just ignore the inv output.
description: |
A macro component which can invert the output of INTp.
The flow chart is just:
+-------+
a0 -->| | +--[ 1| SUMinv ]-> inv
a -->| INTp | |
b0 -->| |--------+----------------> out
b -->| |
icSign>| |
ic -->| |
+-------+
computes:
out: out = integral( a0*a(t) + b0*b(t), t)
inv: inv = -integral( a0*a(t) + b0*b(t), t)
input:
- name: a0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: a
type: analog
- name: b0
type: numeric
description: Potentiometer prefactor
range: [0, 1]
- name: b
type: analog
- name: icSign
type: boolean
description: Sign of initial condition value
- name: ic
type: numeric
description: Value for initial condition
range: [0, 1]
output:
- name: inv
type: analog
description: Actual output of integrator
- name: out
type: analog
description: Output of summer (negation of integrator)
default_inputs:
a: None
b: None
a0: 0
b0: 0
icSign: True
ic: 0
partlist:
MainINT:
type: INTp
input: [ a0, a, b0, b, icSign, ic ]
output: out
SUMinv:
type: SUM
input: { u1: out }
output: inv
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
#
# Pseudo elements (Helpers)
#
# # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # # #
ConstantVoltage:
description: |
This is a pseudo-element only used for allocate a logic +1 and
logic -1 on the XBAR.
Usage examples are given in the partlist with the instances
PlusOne and MinusOne. These parts are subject to be used
also in the actual programs (for the time being), in order to
realize constant inputs for computatational parts. We need
+1 and -1 because the potentiometers only implement range [0,1].
The operation x-0.5 is then realized by the pseudo-code
SUMMER(a=x,a0=1,b=MinusOne,b0=0.5), while x+0.7 is realized by
SUMMER(a=x,a0=1,b=PlusOne,b0=0.7).
computes:
value: value = x
input: [{ name: x, type: analog }]
output: [{ name: value, type: analog }]
NoneType:
description: |
This pseudo-element is only used to implement computational
elements with unconnected inputs. For instance, the pseudo-code
SUMMER(x)=-x is actually implemented as
SUMMER(a=x,a0=1,b=None,b0=0) (the value of b0 is not relevant!).
The compiler will throw out None elements in favour of disabling
the corresponding output line of the XBAR.
The None is also used for slurping input from the DPTs, therefore
they have an input.
computes: nothing
input: [{ name: none, type: analog }]
output: [{ name: none, type: analog }]
default_inputs: { none: 0 }
# Each of the wired hardware needs configuration by the HC
# (which also needs to be configured itself)
wired_parts:
X1:
type: XBAR
address: 0x0040
number_of_config_bytes: 10
# Datasheet of chip AD8113:
# https://www.analog.com/media/en/technical-documentation/data-sheets/AD8113.pdf
topology: Single AD8113
size: [ 16, 16 ]
input_columns:
- PlusOne # 1
- MinusOne # 2
- SUM0-2 # 3
- SUM0-1: out # 4
- SUM0-1: inv # 5
- SUM0-0: out # 6
- SUM0-0: inv # 7
- MLT0-1 # 8
- MLT0-0: out # 9
- MLT0-0: inv # 10
- INT0-2 # 11
- INT0-1: out # 12
- INT0-1: inv # 13
- INT0-0: out # 14
- INT0-0: inv # 15
- None # 16, empty!
output_rows:
- INT0-0: a # 1
- INT0-0: b # 2
- INT0-1: a # 3
- INT0-1: b # 4
- INT0-2: a # 5
- INT0-2: b # 6
- MLT0-0: a # 7
- MLT0-0: b # 8
- MLT0-1: a # 9
- MLT0-1: b # 10
- SUM0-0: a # 11
- SUM0-0: b # 12
- SUM0-1: a # 13
- SUM0-1: b # 14
- SUM0-2: a # 15
- SUM0-2: b # 16
D1:
type: DPT24
address: 0x0060
size: 24
enumeration:
- INT0-0: a0 # 1
- INT0-0: b0 # 2
- INT0-1: a0 # 3
- INT0-1: b0 # 4
- INT0-2: a0 # 5
- INT0-2: b0 # 6
- MLT0-0: a0 # 7
- MLT0-0: b0 # 8
- MLT0-1: a0 # 9
- MLT0-1: b0 # 10
- SUM0-0: a0 # 11
- SUM0-0: b0 # 12
- SUM0-1: a0 # 13
- SUM0-1: b0 # 14
- SUM0-2: a0 # 15
- SUM0-2: b0 # 16
Main:
# A Hybrid Controller has 8 DPTs, 8 digital inputs and
# 8 digital outputs. There can actually be only one HC per
# machine.
type: HC
address: 0x0080
number_of_digital_output_ports: 8
number_of_digital_input_ports: 8
dpt_resolution: 10
dpt_enumeration:
- INT0-0: ic
- INT0-1: ic
- INT0-2: ic
digital_input: []
digital_output:
- INT0-0: icSign
- INT0-1: icSign
- INT0-2: icSign
|